80f6bda437
Add Blackwell/SM100 support * Add compilation for sm100 * Add graph search speeds for Blackwell * Optimize graph search to converge on large NVLink domains * Limit NVLS heads to 32 * Increase various limits to fit large NVLink domains * Add extra checks for IMEX setup, needed for MNNVL * Increase MAXCHANNELS to 64 Extend NVTX instrumentation to track NCCL communicators * Add communicator ID to NVTX traces to allow for correlation between ranks. RAS fixes
140 lines
4.7 KiB
Makefile
140 lines
4.7 KiB
Makefile
#
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# Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
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#
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# See LICENSE.txt for license information
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#
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CUDA_HOME ?= /usr/local/cuda
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PREFIX ?= /usr/local
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VERBOSE ?= 0
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KEEP ?= 0
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DEBUG ?= 0
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ASAN ?= 0
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UBSAN ?= 0
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TRACE ?= 0
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WERROR ?= 0
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PROFAPI ?= 1
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NVTX ?= 1
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RDMA_CORE ?= 0
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NVCC = $(CUDA_HOME)/bin/nvcc
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CUDA_LIB ?= $(CUDA_HOME)/lib64
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CUDA_INC ?= $(CUDA_HOME)/include
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CUDA_VERSION = $(strip $(shell which $(NVCC) >/dev/null && $(NVCC) --version | grep release | sed 's/.*release //' | sed 's/\,.*//'))
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#CUDA_VERSION ?= $(shell ls $(CUDA_LIB)/libcudart.so.* | head -1 | rev | cut -d "." -f -2 | rev)
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CUDA_MAJOR = $(shell echo $(CUDA_VERSION) | cut -d "." -f 1)
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CUDA_MINOR = $(shell echo $(CUDA_VERSION) | cut -d "." -f 2)
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#$(info CUDA_VERSION ${CUDA_MAJOR}.${CUDA_MINOR})
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# You should define NVCC_GENCODE in your environment to the minimal set
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# of archs to reduce compile time.
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CUDA8_GENCODE = -gencode=arch=compute_50,code=sm_50 \
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-gencode=arch=compute_60,code=sm_60 \
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-gencode=arch=compute_61,code=sm_61
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ifeq ($(shell test "0$(CUDA_MAJOR)" -lt 12; echo $$?),0)
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# SM35 is deprecated from CUDA12.0 onwards
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CUDA8_GENCODE += -gencode=arch=compute_35,code=sm_35
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endif
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CUDA9_GENCODE = -gencode=arch=compute_70,code=sm_70
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CUDA11_GENCODE = -gencode=arch=compute_80,code=sm_80
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CUDA12_GENCODE = -gencode=arch=compute_90,code=sm_90
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CUDA13_GENCODE = -gencode=arch=compute_100,code=sm_100 \
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-gencode=arch=compute_120,code=sm_120
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CUDA8_PTX = -gencode=arch=compute_61,code=compute_61
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CUDA9_PTX = -gencode=arch=compute_70,code=compute_70
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CUDA11_PTX = -gencode=arch=compute_80,code=compute_80
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CUDA12_PTX = -gencode=arch=compute_90,code=compute_90
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CUDA13_PTX = -gencode=arch=compute_120,code=compute_120
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ifeq ($(shell test "0$(CUDA_MAJOR)" -eq 12 -a "0$(CUDA_MINOR)" -ge 8 -o "0$(CUDA_MAJOR)" -gt 12; echo $$?),0)
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# Include Blackwell support if we're using CUDA12.8 or above
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NVCC_GENCODE ?= $(CUDA8_GENCODE) $(CUDA9_GENCODE) $(CUDA11_GENCODE) $(CUDA12_GENCODE) $(CUDA13_GENCODE) $(CUDA13_PTX)
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else ifeq ($(shell test "0$(CUDA_MAJOR)" -eq 11 -a "0$(CUDA_MINOR)" -ge 8 -o "0$(CUDA_MAJOR)" -gt 11; echo $$?),0)
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# Include Hopper support if we're using CUDA11.8 or above
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NVCC_GENCODE ?= $(CUDA8_GENCODE) $(CUDA9_GENCODE) $(CUDA11_GENCODE) $(CUDA12_GENCODE) $(CUDA12_PTX)
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else ifeq ($(shell test "0$(CUDA_MAJOR)" -ge 11; echo $$?),0)
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NVCC_GENCODE ?= $(CUDA8_GENCODE) $(CUDA9_GENCODE) $(CUDA11_GENCODE) $(CUDA11_PTX)
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# Include Volta support if we're using CUDA9 or above
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else ifeq ($(shell test "0$(CUDA_MAJOR)" -ge 9; echo $$?),0)
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NVCC_GENCODE ?= $(CUDA8_GENCODE) $(CUDA9_GENCODE) $(CUDA9_PTX)
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else
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NVCC_GENCODE ?= $(CUDA8_GENCODE) $(CUDA8_PTX)
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endif
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$(info NVCC_GENCODE is ${NVCC_GENCODE})
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CXXFLAGS := -DCUDA_MAJOR=$(CUDA_MAJOR) -DCUDA_MINOR=$(CUDA_MINOR) -fPIC -fvisibility=hidden \
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-Wall -Wno-unused-function -Wno-sign-compare -std=c++11 -Wvla \
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-I $(CUDA_INC) \
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$(CXXFLAGS)
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# Maxrregcount needs to be set accordingly to NCCL_MAX_NTHREADS (otherwise it will cause kernel launch errors)
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# 512 : 120, 640 : 96, 768 : 80, 1024 : 60
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# We would not have to set this if we used __launch_bounds__, but this only works on kernels, not on functions.
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NVCUFLAGS := -ccbin $(CXX) $(NVCC_GENCODE) -std=c++11 --expt-extended-lambda -Xptxas -maxrregcount=96 -Xfatbin -compress-all
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# Use addprefix so that we can specify more than one path
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NVLDFLAGS := -L${CUDA_LIB} -lcudart -lrt
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########## GCOV ##########
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GCOV ?= 0 # disable by default.
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GCOV_FLAGS := $(if $(filter 0,${GCOV} ${DEBUG}),,--coverage) # only gcov=1 and debug =1
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CXXFLAGS += ${GCOV_FLAGS}
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NVCUFLAGS += ${GCOV_FLAGS:%=-Xcompiler %}
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LDFLAGS += ${GCOV_FLAGS}
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NVLDFLAGS += ${GCOV_FLAGS:%=-Xcompiler %}
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# $(warning GCOV_FLAGS=${GCOV_FLAGS})
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########## GCOV ##########
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ifeq ($(DEBUG), 0)
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NVCUFLAGS += -O3
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CXXFLAGS += -O3 -g
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else
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NVCUFLAGS += -O0 -G -g
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CXXFLAGS += -O0 -g -ggdb3
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endif
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# Make sure to run with ASAN_OPTIONS=protect_shadow_gap=0 otherwise CUDA will fail with OOM
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ifneq ($(ASAN), 0)
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CXXFLAGS += -fsanitize=address
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LDFLAGS += -fsanitize=address -static-libasan
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NVLDFLAGS += -Xcompiler -fsanitize=address,-static-libasan
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endif
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ifneq ($(UBSAN), 0)
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CXXFLAGS += -fsanitize=undefined
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LDFLAGS += -fsanitize=undefined -static-libubsan
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NVLDFLAGS += -Xcompiler -fsanitize=undefined,-static-libubsan
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endif
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ifneq ($(VERBOSE), 0)
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NVCUFLAGS += -Xptxas -v -Xcompiler -Wall,-Wextra,-Wno-unused-parameter
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CXXFLAGS += -Wall -Wextra
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else
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.SILENT:
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endif
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ifneq ($(TRACE), 0)
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CXXFLAGS += -DENABLE_TRACE
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endif
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ifeq ($(NVTX), 0)
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CXXFLAGS += -DNVTX_DISABLE
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endif
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ifneq ($(WERROR), 0)
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CXXFLAGS += -Werror
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endif
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ifneq ($(KEEP), 0)
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NVCUFLAGS += -keep
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endif
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ifneq ($(PROFAPI), 0)
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CXXFLAGS += -DPROFAPI
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endif
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ifneq ($(RDMA_CORE), 0)
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CXXFLAGS += -DNCCL_BUILD_RDMA_CORE=1
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endif
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